1. Field of the Invention
The present invention relates generally to an improvement in semiconductor delay circuits formed on a semiconductor substrate.
2. Description of the Background Art
With recent advances in semiconductor technology, large scale integrated circuits (LSI) and very large scale integrate circuits (VLSI) have been developed. Such integrated circuits require precise time setting to activate a plurality of elements. In particular, a dynamic RAM (Random Access Memory) takes time from a rise of a word line until detection of an output of a bit line. It is therefore necessary to exactly set timing for activating a sense amplifier.
FIG. 5 is a block diagram of such dynamic RAM. With reference to the drawing, a memory cell array 50 of a dynamic RAM comprises a plurality of word lines WLs, a plurality of bit lines BLs for inputting/outputting data and memory cells MCs arranged at crossing, points between the word lines WLs and the bit lines BLs. The dynamic RAM further comprises a row decoder 51 for activating a word line WL corresponding to an address in response to an external row address signal, a sense amplifier 54 for detecting data from a bit line BL at the time of reading, an output buffer 55 for externally transmitting an output of the sense amplifier 54, and a delay circuit 56. Each memory cell MC comprises an N channel transistor 52 having a gate connected to a word line WL and a drain connected to a bit line BL and a capacitor 53 connected between the source of the N channel transistor 52 and a ground terminal.
In operation, the row address decoder decodes a row address signal to brought a word line WL corresponding to an address to a high level (logical high). The N channel transistor 52 connected to the high level word line WL is turned on. As a result, the data stored in the capacitor 53 is externally transferred through the bit line BL, the sense amplifier 54 and the output buffer 55.
FIG. 6 is a diagram showing a time relation between a level of a word line WL and a level of a bit line BL. T.sub.O represents a time point of a rise of the word line WL, T.sub.l represents a detectable time point, T.sub.r represents a detection time point, T.sub.O -T.sub.r represents a delay time period and T.sub.l -T.sub.r represents a time margin. With reference to the drawing, the time period of T.sub.O -T.sub.l is required from a rise of the word line WL to an appearance of output data on the bit line BL. Therefore, low level (logical low) data might be detected when the sense amplifier 54 is activated at the time point T.sub.O. Thus, the sense amplifier should be activated after a lapse of the time period T.sub.l. In addition, too large a delay time (T.sub.o -T.sub.r) reduces a read rate. It is therefore necessary to precisely set a delay time.
FIG. 7 is a circuit diagram of a delay circuit. With reference to the drawing, a delay circuit 56 comprises an input terminal 5 connected to a word line WL, an output terminal 7 connected to the sense amplifier 54, a first switching circuit A, a second switching circuit B and a capacitor 8 charged/discharged in response to an output of the first switching circuit A. The first switching circuit A comprises a P channel transistor 1 and an N channel transistor 2 each having a gate connected to the input terminal. The P channel transistor 1 has a source connected to a power supply voltage Vcc and a drain connected to a node 6. The N channel transistor 2 has a drain connected to the node 6 and a source grounded. The second switching circuit B comprises a P channel transistor 3 and an N channel transistor 4 each having a gate connected to the node 6. The P channel transistor 3 has a source connected to the power supply Vcc and a drain connected to the output terminal 7. The N channel transistor 4 has a drain connected to the output terminal 7 and a source grounded. The capacitor 8 is connected between the node 6 and the ground terminal.
FIG. 8 is a timing chart of the delay circuit shown in FIG. 7 wherein Vi represents a voltage level of a word line WL, Vn represents a voltage signal of the node 6 and Vout represents a voltage signal of the output terminal 7. Operation of the delay circuit will be described with reference to FIGS. 7 and 8. First, when the input signal Vi attains a high level, the P channel transistor 1 turns off and the N channel transistor 2 turns on. As a result, the electric charges stored in the capacitor 8 are discharged to gradually reduce the potential at the node 6. Then, after a lapse of a fixed time td, the P channel transistor 3 and the N channel transistor 4 attain a threshold voltage V.sub.TH. When the voltages of the transistors become lower than the threshold voltage V.sub.TH (at T.sub.l), the P channel transistor 3 is turned on and the N channel transistor 4 is turned off. As a result, a high level signal is obtained at the output terminal 7. The high level signal is applied to the sense amplifier 54 to activate the same. The data in the memory cell MC is detected.
However, in the delay circuit shown in FIG. 7, the delay time td is changed with a fluctuation of the power supply voltage Vcc. The change in the delay time td is followed by a fluctuation in timing for activating the sense amplifier 54. Such state will be described with reference to FIG. 9.
FIG. 9 is a graph showing a relation between the delay time td and the power supply voltage Vcc. With reference to the drawing, the delay time td is inversely proportional to the power supply voltage Vcc. That is, as the power supply voltage Vcc increases, the delay time td is shortened. This is because the on-resistance of the N channel transistor 2 is reduced as the power supply voltage Vcc increases to increase a high level of an input signal (a level of a word line).